An analog-to-digital converter (ADC) samples input analog data and converts each sample into an output of N-bit digital data. A higher resolution ADC has less quantization noise than a lower resolution ADC. This is illustrated in FIGS. 1A and 1B, in which the digital output of the ADC (solid line) is plotted against the analog input. The dotted line represents the ideal output that perfectly tracks the input, and the grey area represents the quantization noise due to digitization of the analog input. FIG. 1A illustrates the quantization noise of a 3-bit ADC and FIG. 1B illustrates that of a 2-bit ADC. Quantization noise, which is related to ADC resolution, contributes to signal-to-noise ratio (SNR) degradation of a communication link. Thus, the overall SNR requirement of the communication link should be considered when designing an ADC.
For a given sample rate, an ADC circuit having N-bit accuracy consumes power dependent on the resolution. Specifically, an ADC that has more conversion bits typically consumes more power.
Often, to simplify design efforts, the same N-bit resolution is used for all ADCs on a chip. This means that all ADCs on a chip are typically designed to satisfy the highest resolution requirement. However, individual ADCs on the chip may actually have lower resolution requirements. In those cases, least significant bit (LSB) outputs are generated but are not required. This leads to power waste in both the analog and digital domain.